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1/4 STRUCTURE PRODUCT SERIES TYPE PIN ASSIGNMENT BLOCK DIAGRAM PACKAGE Functions Silicon Monolithic Integrated Circuit 8-Channel Switching Regulator Controller for Digital Camera
BDMWV
Fig.1 Fig.2 Fig.3
1.5V minimum input operating Supplies power for the internal circuit by step-up converter(CH1). Contains step-up converter(2ch), step-down converter(4ch), ,inverting (1ch), with 31 step brightness controller for step-up converter(1ch). 5channels contain transistor for synchronous rectifying action mode. 2channels contain FETs for the step-up converter. All channels contain internal compensation. It is possible separately control except CH1 and CH3. Operating frequency 1.2MHz(CH15), 600kHz(CH68). Contains output interception circuit when over load. 2 channels have high side switches with soft start function. Thermally enhanced UQFN044V6060 package(6mm x 6mm, 0.4mm pitch).
Parameter Symbol Voltage Voltage VBAT VHx15 HS78H VLx7,8 IomaxLx1 IomaxHx1 IomaxHx2,5 IomaxHx3,4 IomaxHS78 IomaxLx7,8 Limit 0.37 0.37 0.37 0.322 2.5 1.5 +1.0 +0.8 +1.2 1.0 0.54 (*1) 25+85 55+150 +150 Unit V V V V A A A A A A W
Absolute maximum ratings (Ta=25)
Power Power Supply Input
O
u
t
p
u
t
C
u
r
r
e
n
t
Power Storage Junction
Dissipation Temperature Temperature Tempareture
Pd Topr Tstg Tjmax
Operating
(*1) Without external heat sink, the power dissipation reduces by 4.32mW/ over 25
Recommended operating conditions
Limit TYP 1.0 1.0
CH8 recommended operating conditions
Parameter Power Supply Voltage VREF Pin Connecting Capacitor VREGA Pin Connecting Capacitor
Symbol VBAT CVREF CVREGA
MIN 1.5 0.47 0.47
MAX 5.5 4.7 4.7
Unit V F F Status of this
Limit Parameter Fixed H when determine brightness Fixed L when OFF Fixed H when setting brightness Fixed L when setting brightness Fixed H when EN start-up Fixed L before setting brightness Brightness setting time When start-up Symbo MIN T(ON) T(OFF) T(H) T(L) T(EN) T(CLR) T(SET) 265X1/fosc 256X1/fosc 500 500 4X1/fosc 7X1/fosc TYP MAX 10000 10000 255X1/fosc 2048X1/fosc S S nS nS S S S Unit
document The Japanese version of this document is the official specification. Please use the translation version of this document as a reference to expedite understanding of the official version. If these are any uncertainty in translation version of this document, official version takes priority.
REV. A
2/4
Electrical characteristics Ta=25, VCCOUT=5.0V, VBAT=3V, STB137=3V,UPIC8=2.5V
Limit TYP Limit TYP
Parameter
Symbol
MIN
MAX
Unit
Conditions
Parameter Output Driver
Symbol
MIN
MAX
Unit
Conditions
Internal Regulator VREGA Output Voltage VREGA 2.4 2.5 2.6 V Io=5mA
Prevention Circuit of Miss Operation by Low voltage Input Threshold Vstd1 Voltage Hysteresis Vstd1 Width1 Threshold Vstd2 Voltage 2 Hysteresis Vstd1 Width Short Circuit Protection SCP detect Tscp time Timer start threshold Vtcinv voltage Start-up Circuit Frequency Fstart Start-up VBAT Vst1 Voltage Start-up CH Soft Start Tss1 Time Oscillator Frequency CH15 Frequency CH68 Max duty 2,3,4,5 step-down Max duty 1 step-up Max duty 6,7,8 Error Amp Input Bias current INV threshold 1 INV threshold 2 INV threshold 3 (max) CH6 Output Voltage Line Regulation Output Current When Shorted Soft Start CH2,5 Soft Start Time CH3,4 Soft Start Time CH6 Soft Start Time CH7,8 Soft Start Time Tss2,5 Tss3,4 Tss6 Tss7,8 3.4 1.2 3.4 4.4 4.4 2.2 4.4 5.4 5.4 3.2 5.4 6.6 msec msec msec msec IINV VINV1 VINV2 VINV3 0.79 0.99 370 0 0.80 1.00 400 50 0.81 1.01 430 nA V V mV INV18, NON6=3.0V CH15 CH7,8V CH8I fosc1 fosc2 Dmax1d Dmax1u Dmax2 1.0 0.5 86 86 1.2 0.6 92 92 1.4 0.7 100 96 96 MHz MHz % % % (1) 50 100 2.0 100 2.4 200 2.3 200 2.5 300 V mV V mV VCCOUT Monitor VREGA Monitor
20 0.38
25 0. 48
30 0.58
ms V
INV Monitor CH35
150 1.5
300 -
600 -
kHz V
1.8
3.0
5.3
msec
CH1 Highside SW ON Resistance CH1 Lowside SW ON Resistance CH2 Highside SW ON Resistance CH2 Lowside SW ON Resistance CH3 Highside SW ON Resistance CH3 Lowside SW ON Resistance CH4 Highside SW ON Resistance CH4 Lowside SW ON Resistance CH5 Highside SW ON Resistance CH5 Lowside SW ON Resistance CH6 Driver Output voltage H CH6 Driver Output voltage L CH7,8 NMOS SW ON Resistance CH7,8 Load SW ON Resistance STB137 STB Control voltage Active Not Active
RON1p RON1N RON21p RON21N RON3p RON3N RON4p RON4N RON5p RON5N Vout6H Vout6L RON7,8 N RON7,8p
VCCOUT -1.5
120 80 250 250 250 250 250 250 250 150
VCCOUT -1.0
270 240 400 400 400 400 400 400 400 300 1.0 800 350
m m m m m m m m m m V V m m
Hx1=5V
VCCOUT=5.0V
Hx2=3V
VCCOUT=5.0V Hx3=3V , VCCOUT=5V VCCOUT=5.0V Hx4=3V, VCCOUT=5V VCCOUT=5.0V
Hx5=3V
VCCOUT=5.0V
IOUT6=50mA ,NON6=0.2V
IOUT6=-50mA NON6=-0.2V VCCOUT=5.0V HS7,8H=3V , VCCOUT=5.0V
-
0.5 500 200
VSTBH 1 VSTBL1 RSTB1 VUPIH VUPIL RUPIC1
1.5 -0.3 250 2.1 0 30
400 50
5.5 0.3 700 4.00 0.40 80
V V k V V k
Pull down Resistance UPIC8 UPIC8 Control voltage Active Not Active
Pull down Resistance Circuit Current VBAT terminal H terminal Stand-by Current Lx terminal HS7,8H terminal Circuit Current when start-up VBAT current when voltage supplied for the terminal Circuit Current 1 VBAT current when voltage supplied for the terminal Circuit Current 2 VCCOUT current when voltage supplied for the terminal
ISTB1 ISTB2 ISTB3 ISTB4
-
-
5 5 5 5
A A A A Step down Step up
For Inverting Base Bias Voltage Vref VOUT6 DVLi Ios -6.09 0.2 -6.00 4.0 1.0 -5.91 12.5 V mV mA NON5 12k, 72k (2) VCCOUT=2.85.5V Vref=0V
IST
-
150
450
A
VBAT=1.5V
Icc1
-
45
150
A
VBAT=3.0V
Icc2
-
5.0
9.7
mA
INV18=1.2V , NON6=-0.2V
(1)The protective circuit start working when circuit is operated by 100% duty. So it is possible to use only for transition time shorter than charge time for SCP. (2)Recommend resistor value over 20k between VREF to NON6, because VREF current is under 100uA. This product is not designed for normal operation with in a radioactive environment
REV. A
3/4
Block Diagram
Pin Description
VBAT VCCOUT GND PGND13, 24, 5, 678 VREGA VREF6 OUT6 Hx1,2,3,4,5 Lx1,,2,3,4,5,7,8 HS78H HS7L,HS8L INV1,2,3,4,5,7,8 NON6 INV8I STB13,2,4,5,6,7 UPIC8 Input for battery voltage Power Supply Input Terminal voltage (Input CH1 output voltage) Ground terminal Ground terminal for internal FET VREGA Output CH6 base bias voltage Terminal for connecting gate of CH6 PMOS Input terminal for synchronous High side switch, Power supply for Pch Driver Terminal for connecting inductors Power supply for internal load switch Output terminal for internal load switch Error AMP inverted input Error AMP non-inverted input Error AMP inverted input ON/OFF switch H: operating over 1.5V CH8 ON/OFF switch for CH8 brightness control
Pin Assignment
33 32 31 30 29 28 27 26 25 24 23
INV5 VCCOUT VREGA GND INV2 INV4
INV8I
INV7 NON6 VREF6
34 35 36 37 38 39 40 41 42 43 44
INV8 HS7L HS78H HS8L LX8 PGND678 LX7 OUT6 UPIC8
INV3 INV1 VBAT HX1 HX1 LX1 LX1 PGND13 PGND13 LX3 HX3 STB13
22 21 20 19 18 17 16 15 14 13 12
BD9757MWV
STB5 PGND5 LX5 HX5
1 2 3 4
Fig.1
Package
BDMW
LOT No.
Fig.3
REV. A
HX2 LX2 PGND24 LX4 HX4 STB2 STB4
5 6 7 8 9 10 11
STB7 STB6
Fig.2
4/4
Operation Notes .) Absolute maximum ratings This product is produced with strict quality control. However, the IC may be destroyed if operated beyond its absolute maximum ratings. If the device is destroyed by exceeding the recommended maximum ratings, the failure mode will be difficult to determine. (E.g. short mode, open mode) Therefore, physical protection counter-measures (like fuse) should be implemented when operating conditions beyond the absolute maximum ratings anticipated. .) GND potential Make sure GND is connected at lowest potential. All pins except NON6, must not have voltage below GND. Also, NON6 pin must not have voltage below - 0.3V on start up. .) Setting of heat Make sure that power dissipation does not exceed maximum ratings. .) Pin short and mistake fitting Avoid placing the IC near hot part of the PCB. This may cause damage to IC. Also make sure that the output-to-output and output to GND condition will not happen because this may damage the IC. .) Actions in strong magnetic field Exposing the IC within a strong magnetic field area may cause malfunction. .) Mutual impedance Use short and wide wiring tracks for the main supply and ground to keep the mutual impedance as small as possible. Use inductor and capacitor network to keep the ripple voltage minimum. .) Voltage of STB pin The threshold voltages of STB pin are 0.3V and 1.5V. STB state is set below 0.3V while action state is set beyond 1.5V. The region between 0.3V and 1.5V is not recommended and may cause improper operation. The rise and fall time must be under 10msec. In case to put capacitor to STB pin, it is recommended to use under 0.01F. .) Thermal shutdown circuit (TSD circuit) The IC incorporates a built-in thermal shutdown circuit (TSD circuit). The thermal shutdown circuit (TSD circuit) is designed only to shut the IC off to prevent runaway thermal operation. It is not designed to protect the IC or guarantee its operation. Do not continue to use the IC after operating this circuit or use the IC in an environment where the operation of this circuit is assumed. .)Rush current at the time of power supply injection. An IC which has plural power supplies, or CMOS IC could have momentary rush current at the time of power supply injection. Please take care about power supply coupling capacity and width of power Supply and GND pattern wiring. .)IC Terminal Input This IC is a monolithic IC that has a P- board and P+ isolation for the purpose of keeping distance between elements. A P-N junction is formed between the P-layer and the N-layer of each element, and various types of parasitic elements are then formed. For example, an application where a resistor and a transistor are connected to a terminal (shown in Fig.9): When GND > (terminal A) at the resistor and GND > (terminal B) at the transistor (NPN), the P-N junction operates as a parasitic diode. When GND > (terminal B) at the transistor (NPN), a parasitic NPN transistor operates as a result of the NHayers of other elements in the proximity of the aforementioned parasitic diode. Parasitic elements are structurally inevitable in the IC due to electric potential relationships. The operation of parasitic elements Induces the interference of circuit operations, causing malfunctions and possibly the destruction of the IC. Please be careful not to use the IC in a way that would cause parasitic elements to operate. For example, by applying a voltage that is lower than the GND (P-board) to the input terminal.
Resistor Terminal A
Transistor (NPN) B Terminal B C
E GND Terminal Parasitic element N GND
P N N P-board
P
P N Parasitic element
P N
P P-board
P
Parasitic element
GND
Fig - 9 Simplified structure of a Bipolar IC
REV. A

N
Notice
Notes
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